A 1/1.12-inch $1.4\mu\mathrm{m}$-Pitch 50Mpixel 65/28nm Stacked CMOS Image Sensor using Mulitple Sampling

This paper presents an implementation of a CMOS image sensor with a 65/28 nm Stacked CMOS process. The pixel array consists of 50 Mpixel with
$1.4\ \mu\mathrm{m}$
pixel pitch. The fabricated sensor uses 10-bit column-parallel single slope analog-to-digital converters (ADC). Furthermore, this work uses a new signal dependent multiple sampling technique to reduce noise of a pixel signal. The proposed image sensor achieves a temporal random noise of
$1.4\ \mathrm{e}_{\text{rms}}^{-}$
and a figure-of-merit of analog-to-digital converters (ADCs) achieves 0.477 e-nJ at 50 Mp 18 fps while it consumes 308 mW.