A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier

This paper presents a single-channel two-stage pipelined-SAR ADC with ping-pong switched half of capacitor-digital-to-analog-converter (CDAC) moving the residue amplification into 2
^nd
stage to lighten the timing burden of the 1
^st
stage. Besides, a dynamic open-loop residue amplifier (RA) is employed to improve the energy efficiency and amplification speed. In order to enhance the ADC robustness, the gain variation under the supply and temperature drift are suppressed through the supply-and-temperature compensation bias. The simulation results shows gain variation is less than 5% under the temperature range from -20 °C to 100 °C and supply voltage variation of
$\pm \mathbf{5}\%$
, which ensure the above 56 dB ADC SNDR under process-voltage-temperature (PVT) variation. The ADC is simulated with a 40 nm CMOS process and 1V supply voltage, it achieves 59 dB SNDR with Nyquist input frequency at 1.25 GS/s sampling rate. The power consumption is 5.6mW, leading to a Walden FoM (FoMw) of 6.2 fJ/conversion-step and a Schreier FoM (FoMs) of 169.5 dB.