Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect

An accurate early estimate of the post routing inter-connect parasitics allows for pre-emptive changes to the circuit in earlier phases of the design flow, significantly reducing the design time and effort. In this work, graph based deep regression models are proposed to predict the post routing interconnect capacitance of a circuit by utilizing layout information and the post placement estimates of the interconnect parasitics. The post placement capacitance determined by a commercial physical design tool is used as a baseline for the models, with the mean absolute percentage error (MAPE), the mean absolute error (MAE), and
$R^{2}$
score calculated for comparison. The proposed methodology outperforms the baseline provided by the commercial physical design tools based on results obtained across all trained models, with an average improvement of 23.39% in MAPE, 5.33% in MAE, and 1% in
$R^{2}$
score. The proposed methodology also provides better prediction of the worse case errors as compared to the commercial tool, with the model providing an average improvement of 47.43% in MAPE and 14.31 % in MAE for the nets with the largest 1 % of errors as determined by the tool.