Energy efficiency optimization in Strong-Arm latch-based dynamic comparator by capacitor distribution

In this paper, we present the analysis and optimization method of energy efficiency in a Strong-Arm Latch-based dynamic comparator with additional capacitors to reduce input referred noise (IRN) for high accuracy ADC. Distributing the additional capacitors in integration and regeneration nodes with a specific ratio achieves the best energy efficiency. In the simulation, the comparator achieves an energy efficiency of 198fJ/comparison at an IRN of
$165\mu \text{Vrms}$
, delivering an overall Figure-of-Merit (FoM) of 5.39
$\text{nJ}.\mu \mathrm{V}^{2}$
. The comparator is designed and fabricated in a 65-nm CMOS process and integrated into a SAR ADC. The ADC's measured performance indicates that the comparator's performance is at par with simulated results.