Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs

We present a side-channel attack (SCA) resistant asynchronous-logic (async-logic) AES accelerator that integrates synchronous-logic (sync-logic) Block RAMs (BRAMs) in FPGA as the Substitution-Box. We successfully identify the timing requirements to integrate sync-logic BRAMs in our async-logic AES accelerator and validate our proposed AES accelerator on the Sakura-X FPGA board. With the integration of BRAMs, we improve the resource utilization on FPGA by
$1.6\times$
when compared to the state-of-the-art async-logic AES accelerator, while reducing the power overhead by
$1.4\times$
. We comprehensively evaluate the SCA resistance of our proposed async-logic AES accelerator with 11 attacking models in both time and frequency domains. Based on our evaluations, we show that our proposed async-logic AES accelerator is highly secure against SCA with 30 million EM traces. This is more than
$6000\times$
improvement when compared to the benchmark sync-logic AES accelerator and
$1.5\times$
improvement when compared to the state-of-the-art async-logic AES accelerator.