Investigation of Fabricated CMOS FishboneFETs and TreeFETs With Strained SiGe Nano-Fins on Bulk-Si Substrate

Based on the bulk-Si substrate, the CMOS tree-like FETs including the FishboneFETs with bottom SiGe nano-fin and the TreeFETs without bottom SiGe nano-fin were both designed and experimentally fabricated. The growth of bottom SiGe layer with different Ge fraction following by an accurately selective etching is developed for realizing SiGe nano-fins between Si nanosheets (NSs). The results show that the
${I}_{\text {on}}/{I}_{\text {off}}$
ratio (over
${1}\times {10} ^{{5}}{)}$
and the short channel effects (SCEs) of TreeFETs are effectively optimized, and the effective channel width (
${W}_{\text {eff}}{)}$
is increased for FishboneFETs at the same footprint. Due to the hole conduction advantage of SiGe nano-fin, the on-current (
${I}_{\text {on}}{)}$
of p-type TreeFETs can be higher than that of n-type TreeFETs at
${V}_{\text {OV}}=\vert V_{\text {gs}}$
-
${V}_{\text {th}}\vert =0.5$
V. Meanwhile, the surface scattering of SiGe nano-fin also affects the effective field-effect mobility. As the gate length (
${L}_{\text {g}}$
) scaling, both p-type tree-like FETs exhibit more obvious SCEs than n-type devices, which is maybe the reason of a lower hole barrier occurring by the valence band offset (
$\Delta {E}_{\text {v}}{)}$
obtained in the strained SiGe nano-fin. The results provided one meaningful guide for tree-like FETs optimizing future GAAFET process and CMOS circuits.