Comparative analysis of Hybrid adders with different Technology node using cadence virtuoso

Different Hybrid Full Adder cells with vari-ous design approaches have been proposed by researchers, each with its advantages and disadvantages and implemented in higher technology node. It is therefore important to compare FA cell performance in a systematic manner utilising a standard simulation platform. In this paper, we have given a thorough investigation of FA cells and implemented previous researchers work in 45nm Cadence Virtuoso tool, also validated the results in 90 and 180nm. we examined the performance of 9 existing 1-bit FA cells operating at various voltages and three distinct GPDK technology nodes. All the adders have been compared in terms of delay, power consumption, and power delay product (PDP). And after comparing all the hybrid adders we have observed that hybrid adder proposed by jyoti kandpal provides lower PDP compare to all the adders, adder proposed by jyoti kandpal provides improvement of 59.53%, in terms of PDP by lowering technology node 90nm to 45nm.