Implementation of a Dual-Chamber Pacemaker for Low-Power Applications

In this paper, a Dual Chamber Cardiac Pacemaker is implemented for various heartbeat ranges with the least amount of delay. For diseases like arrhythmia that are life-threatening, pacemakers are required. Maintaining the appropriate heart rate requires a minimum delay between sensing and pacing. The heart of the pacemaker, the timing control unit, the logic unit, and the sensing amplifier make up the pulse generator. The timing control unit and the logic unit make the decision to pace the heart based on the output of a sensing amplifier, thus achieving the demand pacing need. In addition, the VVI, DDD, and rate-responsive approaches of the pacemaker were designed using the VHDL structural approach, considering the pacemaker's timing cycles. The demand pacemaker functions in line with the heart rate of the arrhythmia-afflicted patient, and its range may vary between patients. For the proposed work, a beats-per-minute (bpm) range of 30 to 70 has been chosen. The outcome demonstrates that the proposed work is superior regarding latency, computational complexity, and cost.