Analysis of an Efficient Linear Congruential Generator Architecture for Digital Applications

The factors which assume an essential part in VLSI framework configuration are power, delay and area. In request to carry out quick number-crunching capabilities in numerous information handling processors, Carry Select Adders (CSLAs) are broadly utilized in light of the fact that they are one among large numbers of the quick adders that could be utilized for the high-speed information handling. But in this paper, we are going to use the LCG (linear congruential generator) circuit design and execution in FPGA. Because LCG is easy to implement to check the power, delay and PDP. LCG algorithm is inferred and proposed by Lehmer. In any case, LCG block graph which comprises of D-flip flop, multiplier, adder and mux are intended to measure power, delay and PDP (power delay product) utilizing MOSFET under 32nm, 130nm CMOS technology in HSPICE. The proposed architecture is to implement the LCG design with modified D-flip flop. D-flip flop is adjusted and carried out in LCG circuit design to reduce power, delay and PDP. The proposed D-flip flop achieves the low power, low delay and low PDP than the existing D-flip flop of MOSFET under 130nm, 32nm. However, D-flip flop achieves the low parameters automatically the whole LCG design also achieves the low power, low delay and low PDP than existing system. Overall performance of the proposed system is more efficient in terms of Power, Delay and Power Delay Product