A Modeling and Computational Analysis Method for Multichip DDR Microsystem

The miniaturization of memory systems is of great significance to the miniaturization of aerospace electronic systems, and double data rate (DDR) memory is prone to serious signal integrity (SI) problems due to its high-frequency and high-speed characteristics. Eye simulation analysis is often time-consuming and does not provide insightful guidance for link optimization and requires further circuit modeling and mathematical analysis. Based on a multichip DDR microsystem design, this article proposes a circuit model of links under different topologies by taking a representative multilevel bonding interconnection structure as an example and establishes a mathematical model of DDR received signal through theoretical calculation. At the same time, we summarize the quantitative relationship between the bonding wire parameters and the related SI problems by substituting the actual circuit parameters into the mathematical model formula. Finally, the theoretical analysis results and simulation results are compared and verified through circuit simulation, and the error is analyzed. The results show that the circuit model and theoretical analysis method can quantitatively analyze the SI problem from a mathematical perspective within a certain error range, and the method and conclusion can be used to guide the early design and later optimization of the DDR memory microsystem.