Feasibility Assessment of Metrologies for Thermal Resistance Characterization of Deeply Buried Interfaces between Bonded Silicon Layers

Vertically stacked dies pose thermal management challenges related to increasing power density and the need to conduct heat across interfaces in 3D packages. The thermal resistances across monolithically bonded die interfaces are challenging to characterize in situ due to their low relative magnitude and embedded location in the stack. Such interfaces are buried within the package deeper than the thermal penetration depth of available transient measurement techniques such as time domain thermoreflectance (TDTR) and frequency domain thermoreflectance (FTDR). Steady state techniques such as the reference bar method can measure deeply buried interfaces but require the use of higher temperatures, temperature gradients, and heat fluxes to resolve lower thermal resistances. In this work, we propose and assess the feasibility of thermal metrology techniques for the non-destructive characterization of deeply buried interfaces, targeting thermal contact resistances of the order of 0.01 cm²K/W. We evaluate two different embodiments of the measurement approach. The working principle for both methods includes a combination of non-contact periodic heating and thermal sensing to measure the transient temperature response of a two-layer bonded stack of materials. In the first embodiment, the sample stack is attached over a circular opening in a temperature-controlled heat sink and heated periodically at the center of the suspended zone to create a radial temperature gradient. The second embodiment involves generating a one-dimensional temperature gradient across the stack by periodic heating of one face and steady cooling of the other face. The corresponding amplitude and phase delay of the temperature responses are used to fit for the thermal interfacial resistance, assuming a time-periodic solution for the heat diffusion equation for a system with periodic heating. We compare the measurement sensitivities of both approaches by developing numerical models to simulate the transient temperature profiles across a two-layer bonded silicon stack of known properties and then analyzing the numerical results to infer the interfacial resistance. The one-dimensional gradient approach is found to offer more practically measurable changes in the temperature amplitude compared to the radial spreading approach for thermal interfacial resistances $(R_{th})$ in the range of 0.001 to 0.01 cm² K/W that are buried to a depth of up to a few hundred microns in a two-layer bonded silicon stack.