Evaluating the thermal performance of perovskite SrSnO3 field effect transistors

Given the ever increasing, global electricity consumption, improving the efficiency and reliability of high-power electronics is of paramount importance. Ultra-wide band gap (> 3.4 eV) semiconductors have shown the potential to be used in the next generation of power electronics due to their high breakdown field and mobility. Specifically, high-quality growth of doped strontium stannate perovskite-oxide (SSO) has been recently demonstrated. The thermal properties of this novel material, however, have not been fully investigated and could be the limiting factor (excessive junction temperatures) to maximize device performance. In this study, high resolution $(\approx \mathbf{410}\ \mathbf{nm})$ transient thermoreflectance imaging (TTI) is used to obtain temperature maps of SSO two-terminal devices with varying channel width ($\mathbf{10}\ \boldsymbol{\mu} \mathbf{m}$ to $\mathbf{20}\ \boldsymbol{\mu} \mathbf{m}$). The results show that the device thermal resistance increases by $\approx \mathbf{21} {\%}$ due to the increase in thermal spreading resistance with channel width. The observed trend is further confirmed via transient thermal analysis where the thermal time constant is shown to increase from $\mathbf{20}.\mathbf{9}\ \boldsymbol{\mu}\mathbf{s}$ to $\mathbf{29}.\mathbf{9}\ \boldsymbol{\mu}\mathbf{s}$. Overall, the active layer thicknesses and device geometry (length and width), must be carefully considered to improve device performance and lifetime.