Singular Value Decomposition (SVD) based Thermal Resistance Matrix (TRM) Size Reduction for Fast Optimization of On-Die Floorplan and Temperature Sensor Placement

Thermal-aware design with limited resources essentially requires the accurate Thermal Resistance Matrix (TRM) that represents the relationship between temperature and power with adequate heat transfer structure that include package. The TRM has been widely used for temperature sensor placement and floor-plan optimization in board and on-die design. However, the large size of TRM usually causes the computational burden by consuming a lot of time for design optimization. In this paper, the systematic scheme that reduces the TRM size is being proposed. By using Singular Value Decomposition (SVD), it is presented that the size of TRM can be reduced with K dominant singular values, which can save computational resources to achieve a steady-state temperature map. Thermal resistance matrix, R, can be defined as a rectangular matrix of M x N, where M and N represent monitoring points and power, respectively. The size of [R] can be reduced using [R‘] derived by SVD. While M x N multiplications are required for the original TRM, the reduced matrix achieved from this procedure requires (N+M) x K multiplications when K is the dominant singular values. Since K is usually much smaller than N, (N+M) x K multiplications required by the modified TRM, [R‘], are also much smaller than a number of N x M multiplications required by original [R]. By using this method, several case studies are presented to demonstrate that the proposed systematic scheme is effective and useful for time-efficient optimization of on-die floor-plan and temperature placement when designing System on-Chip (SoC) that include multiple heterogeneous cores.