The Embedded Cooling Silicon 3D Stacking Thermal Test Vehicle

The 3D SiP could effectively miniaturize the multiband RF TR array packages. However, the enormous heat generated by the high-power GaN devices hinders the ultra-compact 3D RF SiP reliability. Although the embedded manifold structure feasibility reduces the inner coolant pathways' construction complexity, the various microstructures on silicon would introduce reliability problems to the module whether during process or utilization. In this study, we proposed an embedded cooling silicon 3D (five layers) stacking TTV to mimic the heat dissipation capacity of the dual-band staking 3D embedded cooling RF SiP microsystem. The residue stress of the bonding process was optimized to guarantee the module's accomplishment. Both the thermography experiment results verify the proposed module has exceptional performance on heat dissipation (heat transfer coefficient: 25 kW/m
^2.
°C) and temperature uniformity (maximum temperature difference: 4.8 °C) utilizing bilayer diversified TTCs (thermal test chip). The experimental results were consistent with the numerical simulation within a tiny error range (± 5 %). Such embedded cooling silicon 3D stacking TTV design and fabrication process provided a constructive canonical form for the future compact multiband high-power RF microsystem.