Design of Multiplex IP Cores for System-level Boundary-scan Test

With the rapid changes in integrated circuit technology, embedded processors and digital integrated circuits have gained extremely wide application, including DSP, MCU, CPU, FPGA, etc. The increasing use of BGA packages for these ICs, combined with the increasing density of single boards, makes traditional test methods no longer applicable. Traditional IC automatic test equipment, single-board or single-link boundary-scan test has long failed to meet the actual use of demand, the actual needs of users are driving the "single-board boundary scan test" to the "system-level boundary-scan test" development. Aiming at the application scenario of system-level boundary-scan testing and the multipoint addressing and link selection function of boundary-scan link bridging chip, this paper designs a multiplex IP core for system-level boundary-scan testing, which can be used to build a system-level boundary-scan testing system and thus realize the system-level application of boundary-scan. The IP core has been simulated and verified to achieve the basic functional replacement of the boundary-scan link bridging chip, achieving the desired design purpose.