A 30-GHz Frequency Doubler Using a Current Folding Technique in 90-nm CMOS Technology

A frequency doubler (FD) with a current folding technique based on a 90-nm CMOS technology is presented in this paper. With Hspice simulation, the power consumption of the FD is 3 mW at a 1.2-V supply voltage. The phase noise of built-in VCO is -105.34 dBc/Hz at 1-MHz offset, and the FOM is -184.65 dB. The tuning range of FD is 31.10 to 33.05 GHz, and HRR21 is large than 39 dBc.