Analog Latch for Time-Mode PWM Signal Processing

In this work, an analog latch is proposed dedicated for the construction of PWM time-mode systems for sampled-data signal processing. In PWM time-mode signal processing the pulse width of a rectangular pulse is the processing variable. The latching time of the analog latch can be easily programmed for lower sampling frequencies without increasing the storing capacitor, which leads to smaller chip area compared to the traditional approach. The proposed structure combines the advantages of analog and digital systems, it has simple structure, and it can lead to modular and versatile hierarchy design. All blocks are designed and verified in TSMC 65nm technology node. The sampling frequency was 625kHz, the accumulated error was around 170ps for a delay 1.6us and current consumption was 23.8μA.