Signal Processing Architecture for Real-time Earthquake Early Warning System

Though significant research has been carried out on software based development of Earthquake Early Warning System (EEWS), relatively less work has been reported so far in literature on VLSI implementation of the same which yields ease in deployment and faster processing. The present research work focuses on the implementation of efficient architectures for seismic signal processing scheme pertaining to onsite EEWS. The framework of the proposed signal processing scheme comprises four sub-modules, namely an enhanced variable step-size (EVSS) adaptive filter for signal denoising, short-time-average/long-time-average (STA/LTA) algorithm for event detection, double numerical integration based drift-free displacement estimation unit, and two-step threshold-based decision making unit for warning generation. Automated detection of the seismic P-wave arrival employing STA/LTA algorithm is prone to suffer from erroneous detection due to high background noise. This research work introduces EVSS Least Mean Square (EVSSLMS) algorithm which outperforms the state-of-the-art adaptive algorithms in terms of convergence speed and steady-state error, and achieves a significant enhancement in detection accuracy (>23%) at low signal-to-noise ratio (SNR) Gaussian noise environment as compared to the similar competing algorithms. However, EVSSLMS is not robust against impulsive noise. Hence, robust EVSS Sign-Sign Algorithm (EVS-SSA) is proposed, which exhibits enhancement in detection accuracy (>22%) under impulsive noise environment over the counterparts. The displacement is estimated by performing double integration. To remove low frequency integration drift, high-pass finite impulse response (FIR) filter is used. A novel matrix grouped common sub-expression elimination (MCSE) algorithm is proposed to minimize the logic operators (LOs) and logic depths (LDs) requirement to design FIR filter. Moreover, a robust two-step threshold based decision making scheme has been incorporated in the EEWS to generate the alarm. In this work, high-speed, low hardware complexity, low power architectures of the aforementioned sub-modules are proposed satisfying the basic necessity of a single sensor based EEWS. The processing time of the proposed system is reasonably small as compared to existing systems. For a single chip solution, the architectures are implemented on FPGA and ASIC platformselectronic document is a "live" template and already defines the components of your paper [title, text, heads, etc.] in its style sheet. *CRITICAL: Do Not Use Symbols, Special Characters, Footnotes, or Math in Paper Title or Abstract. (Abstract)