Reconfigurable VLSI Design Architecture for Deep Learning Established Forelimb and Hindlimb Gesture Recognition for Rehabilitation Application

Recently, a large body of work has revealed a very accurate deep learning established movement categorization algorithmic technique for assistive technology applications. However, minimum seriousness is given to its relative hardware execution. But direct mapping these algorithms onto battery-operated devices is a point of care, edge devices would not yield optimum results necessitating an algorithm-architectural holistic design methodology. In the current study, we offered a method for creating reconfigurable VLSI architectures for deep learning established gesture recognition for rehabilitative technology applications. The ZYNQ ultrascale + MPSoC zcu102 FPGA was used to implement the design. The on- chip power requirements for LoCoMo-Net and MyoNet on FPGA are 3.5 and 5 Watts, respectively. Furthermore, gesture recognition on the FPGA takes both networks at 1.876 ms and 61.988 ms, respectively. The accuracy comparison of the most advanced networks is carried out on the CPU, GPU, FPGA, and ASIC platforms. The suggested architecture was further synthesized utilizing GF 40-nm technology, which resulted in a $2.5\times $ improvement in performance in terms of speed and a 12– $15\times $ decrease in power consumption compared to FPGA in $2.046~mm2$ of space and 300.8423 mW of power at 1.21 V.