Design and Analysis of Sub-Sampling Phase-Locked Loop for Quantum Computing

An 18.2–18.4 GHz sub-sampling PLL (SSPLL) is implemented using Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 90-nm CMOS technology for spin-qubit-based quantum computers. Consuming the power of 64.8 mW and a chip area of 1.9 mm2, the SSPLL delivers a frequency range from 18.2 to 18.4 GHz. In contrast to a classical PLL, the phase detector (PD) and charge pump (CP) noise are not multiplied by
$N^{2}$
, which improves in-band phase noise. When the SSPLL operates at room temperature, it achieves the in-band phase noise of −96 dBc/Hz at 1 MHz frequency offset and far-out phase noise of −123.5 dBc/Hz at 10 MHz frequency offset for the carrier frequency of 18.3 GHz. By estimation, the frequency noise of 36.1 kHzrms can be achieved at 4 K, which almost meets the requirement of a quantum computer adopting Rabi oscillation of 10 MHz and pulsed microwave signal with a pulse duration of 50 ns for the gate operation.