A (0.75–1.13) mW and (2.4–5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology

This brief presents the design of a dual-loop PLL for indoor and outdoor positioning. The proposed architecture is a dual-mode frequency synthesizer. It allows addressing either GNSS or WiFi. Thus, WiFi can assist GNSS for indoor positioning, while GNSS takes care of outdoor positioning. It achieves a high bandwidth with fine resolution without using the fractional-N approach. The PLL operates for the WiFi mode with 57 channels from 5.16 GHz to 5.72 GHz with a 10 MHz channel spacing and for the GNSS mode at frequency bands of GPS, Galileo, GLONASS, Beidou, and IRNSS. The Phase Noise of the designed PLL at 1 MHz offset from the carrier is–97.37 dBc/Hz and–104.58 dBc/Hz for WiFi and GNSS, respectively, and the power consumption is 1.127 mW and 0.749 mW. The total active area is 0.346mm 2. This architecture is the first of its kind for both indoor positioning and outdoor positioning.