Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture

RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple RISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core processors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells (GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories. This paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level (RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based implementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This work also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with different local address spaces.