Towards Buffers as a Scalable Alternative to Registers for Processor-Local Memory

Processors require local memory close to the execution units to bridge the long latencies for accessing the comparatively slow main memory. In particular, traditional processor architectures use register files at the top of the memory hierarchy, and compilers focus on making efficient use of registers as an expensive and sparse resource. To further increase performance, processors exploit instruction level parallelism (ILP) of programs by hosting more and more execution units. However, the limited number of registers and access ports of the register file, together with current code generators, limit the use of ILP. Since increasing the number of registers and the number of read/write ports in the register file increases the circuit size prohibitively, first-in-first-out (FIFO) buffers have been proposed as a better scalable alternative local memory close to the execution units. In this paper, we outline two processor designs that use different types of buffers as local memories, and then prove experimentally that these buffers can be implemented as circuits whose size grows linearly with the buffer depth, while the circuit size of register files grows polynomially of at least degree two. We then discuss the linear (quasi-linear due to the interconnect network) scalability of these novel architectures that replace registers with buffers.