Reconfigurable Hardware Accelerator of Morphological Image Processor

Researchers emphasize the importance of hardware accelerators for mathematical morphology. If there are any issues, the hardware architecture may need to be redesigned. Thus, we propose a novel, reconfigurable hardware architecture with pipeline techniques for acceleration. With the order control register, there is no need to modify the architecture even if different results are expected. Furthermore, the hardware architecture caters to specific purposes instead of requiring a purpose-built hardware design.