Design and Implementation of High Frequency 16-bit full adder on FPGA Families

An adder serves as the main structural component of any contemporary ALU-based processor. It is known that addition is a very fundamental operation that is utilized in almost every computational operation. As the result, the adder circuit's performance will have a significant impact on the processor's performance. The general adders such as half adder, full adder, ripple carry adder, carry skip adder and carry look-ahead adder, fall short of the high- performance processor's expectations in terms of frequency. In this paper, to meet with the desired requirement we proposed a high-frequency 16-bit full adder architecture which has been simulated using Verilog on Xilinx ISE 14.7 tool and implemented on Virtex-5, Virtex-7, Spartan-6 FPGA families and we compared it with the typical 16-bit adder. We have observed that the proposed architecture has frequency enhancement of 468%, 447% & 325% in Spartan-6, Virtex-5 & Virtex-7 respectively than conventional 16-bit adders. Verification is done using QuestaSim 10.4e we achieved 100% coverage.