Design and Simulation of Physical Layer of Peripheral Component Interconnect Express (PCIe) Protocol

PCIe is a communication protocol which is widely used VLSI industry for various applications like desktop, mobile, embedded computing, communication platform and many more. The data transfer between receiver and transmitter in this protocol happens in form of packets. Packet travel from transaction layer then to data link layer after that it goes to physical layer vice versa for receiver side. In this paper physical layer is on focus. Physical layer contains three important modules scrambler/descrambler,8bto10b encoder/decoder and parallel-to-serial and serial-to-parallel. In this paper design of each of the above modules is done using Verilog in Quartus Intel and verification is done on Modelsim.