Design and Verification process of Combinational Adder using UVM Methodology

In very-large-scale integration systems, adders and multipliers are among the arithmetic calculation cells that are most commonly and extensively used. For microprocessors and digital signal processors to effectively apply specialized algorithms like convolution and filtering, efficiency is crucial. A comprehensive guide on arithmetic circuits for digital signal processing is available in Arithmetic Circuits for DSP Applications. For the purpose of testing arithmetic circuit designs, the Universal Verification Methodology (UVM) is the accepted practice. Contrary to earlier methods created by the simulator vendor, the UVM class library greatly automates the system verify language with capabilities like sequences and data automation. In this paper, a benchmark for logic verification using UVM methodology is proposed for combinational adder that demonstrate logic features. The UVM standard's portability and reuse make it possible for the framework of arithmetic circuits to act as a base for upcoming verification methods.