Design and Implementation of Five Stages Piplined RISC Processor on FPGA

This research focuses on designing and implementing a processor with a five-stage pipeline for educational purposes. The proposed processor can execute five 16-bit instructions simultaneously and is designed and simulated using Verilog HDL. It is implemented on a Cyclone IV FPGA on the DE2i-150 design board. The processor is suitable for applications that require high processing speed and low power consumption, including mobile computers, consumer electronics, security systems, and more. This RISC-based processor has simple instructions that consume low power and execute quickly.