Design and Implementation of Single Precision Floating-point Arithmetic Logic Unit for RISC Processor on FPGA

The main purpose of conducting this research is to design and implement a single precision floating-point arithmetic logic unit (ALU) that considered as a part of the math coprocessor. The main advantage of floating-point representation is that it can support more values than fixed-point and integer representations. Summation, Subtraction, multiplication and division are arithmetic functions in these calculations. In this floating-point unit, input must be provided in IEEE-754 format, which is 32 single precision floating point values. The application of This arithmetic unit is located in the math coprocessor. Commonly referred to as reduced instruction set computation (RISC) processor. In this processor, for a signal processing, a value with high accuracy is required and as it is an iterative process, the calculation should be as fast as possible. A fixed-point and integer central processing unit (CPU) can't meet the requirements. The floating-point representation can calculate very large or very small process quickly and accurately. The system designed, verified and implemented with Verilog hardware description language using Intel Altera software tools.