Automation of FSM Verification Using Formal Tools

In today’s design Finite state Machine (FSM) complexity is increasing tremendously. Exhaustive Design Verification (DV) of these FSM’s using simulation at Register Transfer Level (RTL) is challenging due to possible combinations of stimuli. Formal Verification (FV) can efficiently verify them exhaustively. These FSM’s undergo multiple design changes during development cycle and manual DV efforts must be repeated. An automated flow is needed to reduce this manual effort.This paper talks about a novel strategy and a flow called Property Generator (PropGen) to automatically generate System Verilog Assertions (SVA) directly from the FSM design specification captured in a Visio format. It also details various types of assertions generated by this flow. The paper also presents the results of applying the flow to a medium complex design for AI/ML acceleration. The verification effort in terms of time taken to create properties, the time required for the first formal verification report, and property re-generation for design changes is compared between manually written properties. The DUT FSM was verified exhaustively using FV and overall results show significant reduction in FSM DV efforts.