Design and Performance Analysis of 18T Low Power 1-bit Hybrid Full Adder

In Digital Circuits the core component of the Arithmetic logic unit (ALU) is an adder which can perform arithmetic operations thus adders play an essential role in the digital VLSI System. In modern VLSI systems, the entire research moves towards low power and nanotechnology to make the performance of the digital system excellent. The proposed circuit is formed utilizing a hybrid design approach which includes conventional complementary metal-oxide semiconductors, transmission gates and pass transistors (PTs) (C-CMOS). The proposed architecture of hybrid Full Adder (FA) is superior to the existing FA in both power and overall PDP but delay is not much improved. The proposed hybrid FA design architecture is investigated using 90nm technology node on Cadence virtuoso tool. Due to its lower power consumption and optimized value of power delay product, the simulation results proved that the hybrid FA performance analysis is superior and energy efficient. Power Consumption by the proposed single bit hybrid FA is 0.425 watt at the 0.8V supply voltage and input frequency of 100MHz. The proposed design of 1-bit hybrid adder is analyzed at various supply voltage at 90nm technology node with improved performance in both Power delay product (PDP) and power.