NCTFET Device for Low Power VLSI Application

TCAD simulations of Negative Capacitance Tunnel Field-Effect Transistor (NCTFET) of gate length 32 nm has been reported in the proposed work. The electrical characteristics of hetero-gate structure using ferro material has been analyzed by obtaining the on-current (I
ON
), off-current (I
OFF
), sub threshold-slope (SS), and on-off ratio ($I_{ON}/I_{OFF}$). By using hetero-gate, and optimized pockets high on-current of $3.87 \times 10^{-5} A/\mu \mathrm{m}$, low leakage current of $8.02 \times 10^{14}A/\mu \mathrm{m}$, high I$_{ON}/I_{OFF}$ ratio of 10
⁹
, and a steep sub-threshold slope (SS) of 22 mV/dec are obtained for proposed NCTFET. The negative capacitance concept in hetero-gate structure enhances the gate-source voltage, acting like transformer thus resulting in high on-current. A hetero-gate NCTFET’s design, and doping profile can affect its performance in terms of switching speed, power consumption, and noise immunity.