High-Efficient Memristive Genetic Algorithm for Feature Selection

As an NP-hard problem, feature selection often utilizes nature-inspired methods, like the genetic algorithm (GA), to find the partly optimal solution but still suffers from the computational bottleneck under the Von Neumann architecture. In this work, a GA leveraging binary memristors is proposed to solve the feature selection problem for higher efficiency. By mapping the population of the algorithm to the memristor array, the fitness calculation of the algorithm can be efficiently implemented in the analog domain. Moreover, to further improve the algorithm efficiency, the update process of the algorithm iteration mainly containing the crossover operator and mutation operator is implemented based on the memristor state replication and parallel set/reset operations. After analyzing various nonideal factors, such as device variation, ON- OFF ratio, device-struck fault, and so forth, this method shows high robustness and comparable performance to ideal simulation. Compared with traditional CMOS circuits, this method can achieve a speed improvement of
$7000\times $
with 27-fold energy saving in a single cycle.