High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph

This paper proposes a high-performance field programmable VLSI processor (FPVLSI), in which a bit-serial processing element (PE) array is introduced to reduce the complexity of programmable interconnection networks. Therefore, the area and delay of a switch block in the interconnection network can be greatly reduced. Moreover, direct allocation of a control/data flow graph is employed where only a single node is mapped into a PE so that the wiring complexity is greatly reduced. The FPVLSI with 4400 PEs is designed in a 0.35 /spl mu/m CMOS process. The performance of the FPVLSI is evaluated to be 28 times higher than that of the typical FPGA when executing the 16-point FFT.