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Deep Learning Compiler Optimization on Multi-Chiplet Architecture | IEEE Conference Publication | IEEE Xplore

Deep Learning Compiler Optimization on Multi-Chiplet Architecture


Abstract:

Multi-chiplet architecture can provide a high-performance solution for new tasks such as deep learning models. In order to fully utilize chiplets and accelerate the execu...Show More

Abstract:

Multi-chiplet architecture can provide a high-performance solution for new tasks such as deep learning models. In order to fully utilize chiplets and accelerate the execution of deep learning models, we present a deep learning compilation optimization framework for chiplets, and propose a scheduling method based on data dependence. Experiments show that our method improves the compilation efficiency, and the performance of the scheduling scheme is at least 1-2 times higher than the traditional algorithms.
Date of Conference: 11-13 June 2023
Date Added to IEEE Xplore: 07 July 2023
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Conference Location: Hangzhou, China

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