Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array

Compute-in-memory (CIM) is a promising solution to accelerate the extensive multiply-and-accumulate (MAC) operations in deep neural networks (DNNs). Although mixed-signal or analog CIM can achieve high energy efficiency, loss of inference accuracy due to noises and variations is its main drawback. Digital CIM (DCIM) has recently been proposed to achieve both high efficiency and high accuracy. In this work, we first analyze the fundamental properties of DCIM by comparing SRAM-based DCIM with TPU-like systolic array, another popular choice for DNN acceleration. With both designs evaluated in 28-nm process, we observe that DCIM is superior to systolic array in terms of area and power consumption. However, DCIM exhibits poor scalability of latency with increasing array sizes. To mitigate, we propose parallel-input bitwise-weight compute scheme for DCIM shorten its critical path, such that 25% improvement in operating frequency can be obtained with minimal overhead. We then study the systolic DCIM architecture to further enhance the scalability of DCIM. Compared to the compute cores of TPU, systolic DCIM is evaluated to provide 47% and 17% improvements in compute and energy efficiencies.