Accurate Extraction of Minority Carrier Lifetimes—Part I: Transient Methods

A well-defined and high minority carrier lifetime is a key enabler for high-performance optoelectronic detectors. To verify the targeted carrier lifetime various experimental methods such as open circuit voltage decay (OCVD), reverse recovery (RR), and combined current-voltage (
I-V
)/capacitance-voltage (
C-V
) (cIVCV) methods have been proposed in the literature. However, the extracted lifetimes can differ between the techniques, primarily due to geometric effects such as the epitaxial layer thickness. To evaluate the quality of these methods dedicated test structures, i.e., p-n junctions embedded in 20
${ \boldsymbol {\mu }}\text{m}$
epitaxial pp+ silicon wafers, are characterized. In the first part of this work, we present the theoretical framework for describing minority carrier lifetimes in Silicon and review their extraction based on two selected transient methods, i.e., OCVD and RR. Whilst the experimental efforts for these methods are more challenging than for steady-state characterizations, such as cIVCV, the data analysis appears less demanding. To verify the accuracy of the methods, we benchmark them against computer simulations based on the drift-diffusion model with various minority carrier lifetimes. To investigate the influence of the electric field (associated with the lowly-doped epitaxial layer to the highly doped substrate transition) on the extracted carrier lifetimes, simulations with and without substrate are compared, and a strong influence of this low-high transition on the extracted parameters is observed. This effect can be modeled with an effective surface recombination velocity associated with the low-high transition region. Additionally, experimental data of the aforementioned structure are analyzed and compared to the computer simulations. We can show that OCVD and RR are excellent candidates for the extraction of effective carrier lifetimes on epitaxial p-n junctions.