Inverse Design of On-Chip Interconnect via Transfer Learning-Based Deep Neural Networks

on-chip interconnects are very important in both integrated circuits and systems, affecting signal transmission directly. To design the interconnects with better performance, designers usually rely on heuristic methods and even rules of thumb with high labor resources. To alleviate this issue, transfer learning-based deep neural networks (TL-DNNs) are proposed to realize the inverse and fully-automatic design of the on-chip interconnects. Such a TL-DNN-based surrogate model consists of two deep neural networks (DNNs). The first DNN is employed to map the performance parameters to the geometric parameters in the equivalent circuit space, where the trained hyperparameters of the first DNN are transferred to the second DNN model. Furthermore, 300 datasets from the in-house electromagnetic (EM) parallel solver space are generated and used to train the second DNN, with 3000 datasets used for testing. Compared with the DNN-based and deep hybrid neural network (HDNN)-based inverse design methods, the proposed method not only achieves a high testing accuracy (93.67%), but also requires only 6.15 h of modeling time. In addition, the well-trained model has the ability to achieve the desired design specification within a fraction of a second, compared to the hours–days–weeks of the forward design approach. An elaborate interconnect prototype is fabricated, and its measured results fully satisfy the performance demands. It is expected that the proposed modeling scheme can be used for the design of many interconnects.