D-Band On-Chip Couplers With Multilayered Slow-Wave Unit Cell in Standard CMOS Process

Millimeter-wave (mm-Wave) and terahertz (THz) technologies are promising for many emerging applications including 6G communication. At such high frequencies, it is very challenging to accurately and efficiently integrate discrete passive circuits with tiny silicon chips. Therefore, it is meaningful to explore the feasibility of directly integrating passive circuits into silicon chips, to achieve mm-Wave and THz system-on-chip (SoC) with full integration, low interconnection loss and affordable cost. Driven by this goal for D-band (110–170 GHz) SoC, this paper presents two couplers in standard CMOS process, i.e., 180° rat-race and 90° branch-line couplers. To reduce the footprint, multilayered slow-wave unit cell is proposed to efficiently use back-end-of-lines (BEOLs) in standard silicon process. Compared with conventional microstrip line, the proposed unit cell increases the relative permittivity by 2.4 times, and achieves 44.2% length reduction at 140GHz. Both theoretically modeled and full-wave simulated results indicate that, the proposed multilayered unit cell features distinct slow-wave effect, to slow down the phase velocity of electromagnetic waves, and therefore reduce the size of two couplers to 0.038 mm2 and 0.04 mm2, respectively. To the best knowledge of the authors, this is the first time to use multilayered slow-wave unit cell for D-band CMOS couplers, which is a basic block of mm-Wave and THz transceiver chip.