Improved Scalability of Negative Capacitance Junctionless Transistors With Underlap Design

Through physical insights and well-calibrated simulations, this work reports on the scalability comparison of negative capacitance (NC) junctionless (JL) and inversion mode (IM) transistors for the technology node (TN) down to 1.5 nm. Due to different operating mechanisms, the distinction in NC effect in JL and IM devices is investigated. Results showcased that NCJL transistors with an optimal underlap (~6 nm) outperform NCIM devices as
$\sim 2.5\times 10^{2}$
times lower OFF-current (
${I} _{\text {OFF}}$
) along with higher ON-current (
${I} _{\text {ON}}$
) is achieved in NCJL device at a 1.5-nm node. This work provides new opportunities and comprehensively highlights the potential benefits of underlap design in reducing
${I} _{\text {OFF}}$
without compromising
${I} _{\text {ON}}$
in NCJL devices at scaled TNs.