An Area Optimized Floating-Point Coprocessor for RISC-V Processor

In this paper, we outline the design and development of an area optimized Floating-Point Unit (FPU) in accordance with the IEEE 754-2008 standard. This FPU acts as a coprocessor for RISC-V ISA based VEGA processor. The FPU supports both in-order and out-of-order execution of 58 RISC-V floating-point instructions with partial pipelining.