API Gateway Optimization Architecture Based on Heterogeneous Hardware Acceleration

With the development of Internet technology, more and more businesses are developing towards microservices. As the entrance of request traffic, the API gateway carries a huge load. It needs to avoid becoming the bottleneck of the entire system and needs to have high performance. At the same time, the traditional gateway implementation method strongly relies on the processing power of the CPU itself. However, with the slowdown of CPU Moore’s Law and the sharp increase of business types and data volume, the CPU’s performance improvement on API gateways is limited. In response to these problems, this paper proposes a heterogeneous hardware-accelerated API gateway architecture, which uses heterogeneous hardware devices such as QAT to offload functions such as HTTPS and Gzip of the API gateway, thereby greatly improving the overall gateway performance, and significantly reduce CPU usage and improve overall system utilization.