Optimization Strategies for Low-Latency 5G NR LDPC Decoding on General Purpose Processor

In recent years, with the progression of the computational abilities of General-Purpose Processors (GPPs), there has been a heightened interest in the implementation of software Low-Density Parity-Check (LDPC) decoders. This investigation provides a comprehensive analysis of the most effective strategies for optimizing the decoding latency of 5G LDPC on GPPs. Our proposed optimization mechanisms consist of the implementation of Advanced Vector Extensions 512 (AVX-512) instructions in computationally intensive routines and the application of code transformation techniques, specifically optimization through unrolling to tackle the primary computational challenges and minimize the overall latency of the decoder. To assess the efficiency of our proposed techniques, thorough simulations were carried out to determine the decoding time. Our findings indicate that the implementation of the aforementioned optimization techniques on computational routines causing time bottlenecks can lead to a significant reduction of at least 30% in computational delay, even under unfavorable conditions. This discovery demonstrates the feasibility of developing a low-latency software 5G NR LDPC decoder on an x86 architecture.