Study on optimization of image lag process based on 4T CMOS image sensor

The trap energy level and electric potential deviations caused by the presence of non-ideal effects in CMOS image sensor pixel cells during the manufacturing process often lead to incomplete charge transfer during the transfer of photo-generated signal charge from the PPD to the FD, resulting in image lag from the residual charge trapped in the PD, thus affects the sensor imaging effect. The commonest method to improve the image lag phenomenon is to optimize individual process parameters. In this paper, a more systematic process parameter optimization method which is simulated and optimized for the image lag aimed at two aspects: the threshold voltage implantation adjustment of TG channel and the implantation dose of N-type impurities in PPD is proposed. The optimal process state and operating conditions for minimizing image drag are obtained as follows: TG channel implantation dose 8.0e12 cm-2 and PPD N impurity implantation dose 3.0e12 cm-2. The research method in this paper provides theoretical guidelines for optimizing and improving the performance of 4T pixel design for CMOS image sensor.