Design and implementation of Modbus serial line Server RTU VIP

Verification is a crucial phase in the design cycle of an ASIC or FPGA. As the digital design complexity keeps increasing, its verification complexity increases as well. In this scenario, the concept of VIP (Verification intellectual property) emerged, which is a pre-packaged set of code used for verification that could be easily plugged into a simulation environment to shorten the verification cycle and increase the coverage.Modbus RTU (Remote Terminal Unit) is the serial version of Modbus data communication protocol. Modbus serial line server RTU VIP is an endeavour to optimize the efforts dispensed in a FPGA/ ASIC project implementation. The algorithm for the Modbus VIP is designed and implemented in Universal Verification Methodology. The Modbus VIP brings in automation to the cumbersome testing process and cut short the lengthy man hours spend in simulation result analysis and debugging. It addresses the challenges in the verification of a Modbus implementation in terms of functional and structural coverage, efficient bug detection, effective debugging and drastically lessen the verification effort, reduce the overall product cycle time and thereby, the product cost.