A 1.25-MHz-BW, 83-dB SNDR Pipelined Noise-Shaping SAR ADC With MASH 2-2 Structure and kT/C Noise Cancellation

This brief presents a 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) using a 2–2 multistage noise-shaping (MASH) structure. By combining pipeline timing with kT/C noise cancellation and dynamic amplifier (DA) sharing techniques, a high-order noise-shaping SAR with reduced hardware cost and optimized timing is achieved. Fabricated in a 65-nm CMOS technology, the prototype NS-SAR ADC consumes
$335~\mu \text{W}$
under a 1.2-V supply voltage when operating at a 20-MS/s sampling rate. An 83-dB signal-to-noise-and-distortion ratio (SNDR) is measured for a 0.367-MHz sinusoid input under an oversampling ratio (OSR) of 8. It achieves a peak Schreier FoM of 178 dB and the core circuit occupies a 0.08-mm2 area.