Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS

The impact of variability in CMOS technology increases with scaling and low-voltage operation, where conventional design flows need to manage large design margins to ensure an acceptable yield. In this article, we present a novel methodology to improve the digital circuit’s energy efficiency binomial eliminating the unnecessary margins and guaranteeing the same
$4\sigma $
production yield. The proposed methodology is based on an automated in situ error prediction strategy fully compatible with a conventional industrial design flow. The main field of application is the design of generic DSP blocks. As such, the methodology is demonstrated on a 22-nm CMOS Viterbi decoder. Results show that with this methodology, we can safely recover more than 95% of the conventional energy design margin, improving the energy efficiency by 30%–40% with a low area overhead of 6%. Fabricated and tested circuits operate with a maximum of 16 mV voltage margin, providing an additional maximum energy benefit of 55% compared to a replica-based adaptive voltage scaling (AVS) system.