An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box–Muller Method

In this paper, we introduce an accurate, efficient, and optimized design and implementation of a Gaussian pseudo random number generator (PRNG) on a field-programmable gate array (FPGA) platform. A second-order segmented Box-Muller (S
²
BM) transformation is proposed as an alternative approach to our previously presented segmented Box–Muller (S-BM) transformation. S
²
BM transformation targets two goals simultaneously: enhancing accuracy and improving efficiency by introducing two new upgrades to the S-BM transformation. The first upgrade was performed by splitting each segment into two parts, the body and tail, using two different Box–Muller (BM) transformation steps. The second upgrade was made by producing two uncorrelated samples per clock cycle with small additional FPGA logic. The achieved FPGA implementation scores prove that the designed 19-bit S
²
BM Gaussian PRNG generator offers an improvement of 21% and 29% in efficiency over the S-BM within the ranges of
$\pm 7.81\sigma $
and
$\pm 9.561\sigma $
respectively, when implemented on the cost-optimized Xilinx Spartan-6 devices (XC6SLX75T). An improvement of 86% and 149% in efficiency are obtained respectively, over the Central Limit Theorem (CTL) Hadamard transformation and the Multihat transformation. Furthermore, the obtained results and performance confirmed the superiority of the S
²
BM transformation in terms of accuracy and efficiency compared with the existing GRN generator architectures.