Performance Analysis and Optimization of Distributed Arithmetic-Based Convolutional Algorithms for FIR Filters on FPGA

Distributed arithmetic (DA) implementation for finite impulse response (FIR) filters on field-programmable gate arrays (FPGAs) is highly desirable in digital signal processing due to its fast computational speed and low power consumption. However, traditional LUT-based DA implementation on FPGAs is challenging because of its high memory space requirements. To overcome this challenge, LUT-partition and MUX-incorporation techniques have been proposed to reduce memory space, but they also increase the FPGA resource utilization. Furthermore, the inherent serial nature of DA computing can limit data throughput. Parallel processing of multiple bits can improve computational performance but at the cost of chip area. Therefore, it is beneficial to combine optimization methods to achieve desired performance. This paper proposes a comprehensive approach for optimizing memory space, computational performance, and chip area by analyzing different LUT partitions and incorporating MUX configurations. The proposed method is evaluated on a Xilinx Zynq 7010 FPGA, demonstrating its effectiveness.