A Compact All-MOSFETs PVT-compensated Current Reference with Untrimmed 0.88%-(σ/μ)

An excessive sensitivity to PVT variations may represent a considerable issue of a Current Reference (CR) circuit, possibly resulting in poor reliability of CR-supplied systems. CR area occupation is also critical in size-constrained designs. In this work, we present and analyze a compact all-MOSFETs CR topology. Implemented in 0.18 $\mu\mathrm{m}$ CMOS, the proposed design generates a 946 nA reference current. Simulated temperature coefficient and line sensitivity are equal to 318 ppm/°C and 5.12%/V, respectively. Besides, based on process sensitivity analyses, the reference current exhibited a relative standard deviation equal to 0.88%, which is competitive with state-of-the-art solutions.